1. Field of the Invention
The present invention relates to a digital logic test method, and more particularly, to a digital logic test method to systematically approach functional coverage completely and related apparatus and system.
2. Description of the Prior Art
About one and a half decades ago the state of the art in DRAMs was 64 k bytes, a typical personal computer (PC) was implemented with about 60 to 100 dual in-line package (DIPs), and the VAX11/780 was a favorite platform for electronic design automation (EDA) developers. Now, CPU performance and DRAM capacity have increased by more than three orders of magnitude. More complex ICs perform computation, control, and communications in myriad applications. With contemporary EDA tools, one logic designer can create complex digital designs that formerly required a team of a half dozen logic designers or more.
Though comprising fewer integrated circuits, a modern PC can still perform a variety of astonishing functions. Without any doubts, a modern integrated circuit has an inner circuit far more complicated than that of the DIP chip.
The explosive advancement of electronics technologies is not without problems. For example, digital logic test and verification present major hurdles to continued progress. In a typical digital logic test method, stimuli (called test patterns or test vectors) generated by simulators, which can be compiled or interrupted by hardware design language (HDL), are applied to the pins of a device under-test (DUT), and the response is evaluated. If we know what the expected response is from the correctly operating device, we can compare it to the response of the DUT to determine if the DUT is responding correctly. The increase in size and complexity of circuits on a chip, often with little or no increase in the number of I/O pins accordingly, creates a testing bottleneck. Much more logic functions must be controlled and observed with the same number of I/O pins, making it more difficult to test the chip. According to such a scenario, testing a chip of this size performed by logic testers approaches the amount of effort required to design it. Moreover, for some very complicated and hard to test an integrated circuit, such as a sequential circuit, the logic testers have to ask the logic designers to simplify the integrated circuit. Accordingly, a design-for-test EDA device, which has the capabilities to design and to test, comes to the market. In the process to design an integrated circuit, the logic designers have to take the testability of the integrated circuit into account seriously.
Defects may appear in a single integrated circuit sporadically or in a series of integrated circuits systematically. That the defects sporadically appears in a single integrated circuit will not bring any impact on the creditability of the company who design the integrated circuit, as long as the integrated circuit exceeds an acceptable quality level (AQL) set by the company. However, a company who designs the integrated circuit having the systematical defects may live a tough life. Therefore, new test strategies are emerging in response to test problems arising from these increasingly complex devices, and greater emphasis is placed on finding defects as early as possible in the manufacturing as well as the design cycle.
In recent years, a variety of digital logic test methods to test integrated circuits have come to the market, for example, a logic and fault simulation algorithm, an automatic test pattern generation (ATPG) designed to test combinational circuits, an iterative test generator (ITG) technique designed to test sequential circuits, and a GALloping PATern (GALPAT) technique designed to test memory, and so on. According to the variations of the test patterns these digital logic test methods apply to the DUT, a function coverage technique and a code coverage technique are two of the most popular digital logic test methods used by the logic testers.
The advantage of the code coverage technique is that it can scope a test range easily, and be applied to a register transfer level (RTL). As soon as a bug appears, the code coverage technique corrects the RTL immediately, and keeps on executing corresponding test processes. The code coverage technique can be used to measure a block coverage, an expression coverage, a path coverage, and a branch coverage, which is exclusive for a state machine.
In statistics, since the logic testers do not have the capability to design all of the test patterns a code coverage has to cover, the effectiveness of the code coverage technique is from 80 percents when testing larger modules to 90 percents when testing smaller modules. The code coverage technique with such a high effectiveness can promise nothing but a higher credibility of the integrated circuit under test at most, and whether the integrated circuit is flawless is still uncertain. Moreover, the code coverage technique lacks the capability to look for errors hidden between sub-modules.
In general, the code coverage technique is applied to a preliminary test for an integrated circuit chip, so as to find any gross deficiencies of the integrated circuit chip as early as possible. The code coverage technique analyzes a completeness of test patterns generated by a random simulator to test an integrated circuit chip. The logic designers and logic testers design a test pattern according to the characteristics of the integrated circuit chip, and read any results from the random simulator. As the number of electronic components, such as transistors and registers, is becoming larger and larger, the random simulator has to generate more complicated test patterns to test the integrated circuit chip accordingly, and in consequence, the code coverage technique analyzes the random simulator generates incomplete test patterns.
In addition to provide a test information abundant enough to cover any variations of all the variables of an integrate circuit chip precisely, a good logic test method has to acquire the test information without any difficulties. That is to say, in addition to the logic designers, who are familiar with the integrated circuit chip, anyone can design a test pattern exclusively for the integrated circuit chip easily with such a good logic test method, and acquire the test information corresponding to the integrated circuit chip after the logic test method is executed. In regard to the code coverage technique for an example, the logic designers, who have in person participated in the design of the integrated circuit chip, surely have the capability to design a test pattern to cover all the functionalities of the integrated circuit chip as completely as possible. However, imposing such a difficult task on the logic testers, who do not quite understand the integrated circuit chip, is not reasonable.